library ieee;
use ieee.std_logic_1164.all;
use work.all;

architecture STRUCTURAL of dFlipFlop is
	
	component nand2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component; 
	
	component nand3
	
	port(a,b,c : in bit;
		z : out bit
	);
	
	end component; 
	
	for all : nand2 use entity work.NAND2;
	for all : nand3 use entity work.NAND3;
	
	signal sigVec : bit_vector(5 downTo 0);
	
begin

	ND0 : nand2  port map(sigVec(3), sigVec(1), sigVec(0));
	ND1 : nand2  port map(sigVec(0), clk, sigVec(1));
	ND2 : nand3  port map(sigVec(1), clk, sigVec(3), sigVec(2));
	ND3 : nand2 port map(sigVec(2), d, sigVec(3));
	
	ND4 : nand2 port map(sigVec(1), sigVec(5), sigVec(4)); 
	ND5 : nand2 port map(sigVec(4), sigVec(2), sigVec(5));
	
	q <= sigVec(4) AND clr_al after 2 ns;
	qn <= sigVec(5) AND clr_al after 2 ns;
	
end architecture STRUCTURAL;